M16CSLASH29 datasheet(308/499 Pages) RENESAS

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16. MULTI-MASTER I2C bus INTERFACE

page 284

16.14 Precautions

(1) Access to the registers of I2C bus interface circuit

The following is precautions when read or write the control registers of I2C bus interface circuit

•S00 register

Do not rewrite the S00 register during data transfer. If the bits in the S00 register are rewritten, the bit

counter for transfer is reset and data may not be transferred successfully.

•S1D0 register

Bits BC2 o BC0 are set to 0002 when START condition is detected or when 1-byte data transfer is

completed. Do not read or write the S1D0 register at this timing. Otherwise, data may be read or

written unsuccessfully. Figure 16.22 and Figure 16.23 show the bit counter reset timing.

•S20 register

Do not rewrite the S20 register except the ACKBIT bit during transfer. If the bits in the S20 register

except ACKBIT bit are rewritten, the I2C bus clock circuit is reset and data may be transferred incom-

pletely.

•S3D0 register

Rewrite bits ICK4 to ICK0 in the S3D0 register when the ES0 bit in the S1D0 register is set to 0 (I2C bus

interface is disabled). When the WIT bit is read, the internal WAIT flag is read. Therefore, do not use

the bit managing instruction(read-modify-write instruction) to access the S3D0 register.

•S10 register

Do not use the bit managing instruction (read-modify-write instruction) because all bits in the S10

communication mode select bits, bits MST and TRX, are changing their value. Otherwise, data may be

read or written unsuccessfully. Figure16.21 to Figure 16.23 show the timing when bits MST and TRX

change.

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