M32CSLASH8A datasheet(265/372 Pages) RENESAS

265 / 372 page

M32C/8A Group

17. Serial Interfaces

Rev.1.00

Jul 15, 2007

Page 248 of 352

REJ09B0385-0100

Figure 17.33

SIM Interface Operation

Data is transfer from UiTB register

to UARTi transmit shift register

"L" level is sent back from the SIM card since parity error has occurred

Data is set in UiTB register

Stop bit

Parity bit

Start bit

TE bit in the

UiC1 register

The above applies under the following conditions:

- UiMR register: PRYE bit = 1 (parity enabled), STPS bit = 0 (1 stop bit)

- UiC1 register: UiIRS bit = 1 (transmit interrupt is generated at the transmit completion)

Internal transmit

clock

TI bit in the UiC1

TXDi output

TXEPT bit in the

UiC0 register

IR bit in the

SiTIC register

D1 D2 D3 D4 D5 D6

D0 D1 D2 D3 D4 D5 D6

(2) Receive operation

RE bit in the

UiC1 register

The above applies under the following conditions:

- UiMR register: PRYE bit = 1 (parity enabled), STPS bit = 0 (1 stop bit)

Transmit

waveform sent by

transmitting device

RI bit in the

UiC1 register

IR bit in the SiRIC

Set to 0 by an interrupt request acknowledgement or by program

16( m+ 1)

TC =

i = 0 to 4

Internal receive

clock

“H”

“L”

fj: f1, f8, f2n(4)

Parity error signal

sent back from

receiving device

Signal line level(2)

D0 D1 D2 D3 D4 D5 D6

TXDi ouput

“H”

“L”

(1) Transmit operation

Signal line level(3)

(note 1)

Detect the level in interrupt routine

Stop bit

Parity bit

Start bit

D0 D1 D2 D3 D4 D5 D6

Read from the UiRB register

"L" level is sent back from the SIM card since parity error has occurred

NOTES:

1. Transmit operation is started when UiBRG overflows after data is set in the UiTB register in the indicated timing.

2. Because pins TXDi and RXDi are connected, a composite waveform, consisting of transmit waveform from the TXDi pin and parity error signal from the

receiving device, is generated.

3. Because pins TXDi and RXDi are connected, a composite waveform consisting of transmit waveform from the transmitting device and parity error

signal from the TXDi pin, is generated.

4. Bits CNT3 to CNT0 in the TCSPR register selects no division (n = 0) or divide-by-2n (n = 1 to 15).

Set to 0 by an interrupt request acknowledgement or by program

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