M32CSLASH8A datasheet(266/372 Pages) RENESAS

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M32C/8A Group

17. Serial Interfaces

Rev.1.00

Jul 15, 2007

Page 249 of 352

REJ09B0385-0100

Figure 17.34

SIM Interface Connection

17.1.6.1 Parity Error Signal Output Function

When the UiERE bit in the UiC1 register (i = 0 to 4) is set to 1 (error signal output), the parity error signal

output is enabled. The parity error signal is output when a parity error is detected upon receiving data, and an

“L” signal is output from the TXDi pin in the timing shown in Figure 17.35. If the UiRB register is read while

a parity error signal is output, the PER bit in the UiRB register is set to 0 (parity error not occurred) and the

TXDi pin level becomes back to “H”.

To determine whether the parity error signal is output or not, read the port that shares a pin with the RXDi pin in

the transmission complete interrupt routine.

Figure 17.35

Parity Error Signal Output Timing

MCU

TXDi

RXDi

i = 0 to 4

SIM card

NOTE:

1. Connect the TXDi and RXDi pins and pull up these pins.

Receive

operation

complete flag

i = 0 to 4

ST: Start bit

P: Even parity bit

SP: Stop bit

RXDi

TXDi

"H"

"L"

"H"

"L"

Hi-Z

The above applies under direct format conditions:

- UiMR register: PRY bit = 1 (odd parity)

- UiC0 register: UFORM bit = 0 (LSB first)

- UiC1 register: UiLCH bit = 0 (not inverted)

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