M32CSLASH8B datasheet(403/406 Pages) RENESAS

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REVISION HISTORY

M32C/8B Group Hardware Manual

Rev.

Date

Description

Page

Summary

0.10

May 15, 2008

−

First Edition issued

0.50

Oct 31, 2008

3, 5

Overview

• Table 1.2, 1.4 Specifications Current consumption added, modified

• Table 1.13 Pin Functions (3/3) A/D converter

AN0_0 to AN0_7, AN2_0 to AN2_7 supply voltage changed to VCC2

Special Function Registers (Suffers)

• Table 4.2 Note is added to Page mode wait control register 0, 1

• Table 4.7 Address changed from “044Ch” to “034Ch”

Reset

• Table 5.1 Note 4 changed from “P5_5(EPM)” to “EPM(P5_5)”

Power Supply Voltage Monitor Function

• Figure 6.3 DVCR register Note 2: Vdet(F), Vdet(R) values are added

Clock Generation Function

• Figure 9.4 MCD Register Note 2 modified

• 9.5.1.3 Low-Speed Mode Text revised

• 9.5.1.4 Low-Power Consumption Mode Text revised

• Table 9.8 “the clock input to the CLKi pin (i = 0 to 6)” changed to “the

external clock”

• Figure 9.19 Note 1 text revised

108

110

Interrupts

• 11.5.1 Fixed Vector Table Text revised

• Figure 11.8 Diagram on the right: text changed from “Stack state before...”

to “Stack state after...”

• Figure 11.10 “Interrupt request level determination output” changed to

“Request signal used to wake-up from wait mode/stop mode”

185

Three-Phase Motor Control Timer Function

• Figure 16.7 TB2SC register Note 1 deleted

201

202

218-247

248

Serial Interfaces

• Figure 17.5 DINC bit changed from “Serial input pin..” to “Serial I/O pin..”

• Figure 17.6 UiSMR4 register Note 5 added

• Figure 17.11 to 17.32 Flow charts: “Initial setting start” to “Start”, “Initial

setting end” to “End”

• Figure 17.33 (2) Text changed to “TXDi pin outputs “L” level since...”

263

267

A/D Converter

• Table 18.8 Start condition “retrigger of external trigger is invalid” deleted

• Table 18.11 Note 2 revised

• 18.2.4 Text modified, added

281-283

Programmable I/O Ports

• Figures 22.1 to 22.3 Figures modified

308

311

315

317

Flash Memory

• 23.6.1 CPU Rewrite Mode text added

• Table 23.5 Read protect bit status, 2nd bus cycle changed “BA1” to “PBA”

• Figure 23.12 Note 3 and 4 added

• (9) Text changed from “any even address” to “the protect bit address”

“The flash memory enters...by reading a protect bit address.” added

• Figure 23.14 Text changed from “any even address” to “protect bit

address”

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