M32CSLASH8B datasheet(90/406 Pages) RENESAS

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Under development

M32C/8B Group

9. Clock Generation Circuits

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 73 of 385

Figure 9.8

TCSPR Register, CPSRF Register

b7 b6 b5 b4

Count Source Prescaler Register

Symbol

TCSPR

Address

035Fh

Bit Symbol

Bit Name

CNT0

After Reset(2)

0XXX 0000b

NOTES:

1. Set bits CNT3 to CNT0 after the CST bit is set to 0.

2. The TCSPR register maintains values set before reset, even after the software reset or watchdog timer reset has been performed.

Function

Division rate select bits(1)

CNT1

CNT2

If the setting value is n, f2n is the main clock,

on-chip oscillator clock, or PLL clock divided

by 2n.

When n is set to 0, no division is selected

CNT3

−

(b6-b4)

−

CST

Operation enable bit

Reserved bits

Read as undefined value

0: Divider stops

1: Divider operates

Clock Prescaler Reset Register

b7 b6 b5 b4

Symbol

CPSRF

Address

0341h

Bit Symbol

Bit Name

−

(b6-b0)

After Reset

0XXX XXXXb

Function

Unimplemented.

Write 0. Read as undefined value.

CPSR

−

Clock prescaler reset bit

When the CPSR bit is set to 1, a divider for

fC32 is reset. Read as 0.

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