M32CSLASH8B datasheet(50/406 Pages) RENESAS

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Under development

M32C/8B Group

5. Reset

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 33 of 385

Reset

Hardware reset, software reset and watchdog timer reset are implemented to reset the MCU.

5.1

Hardware Reset

Pins, CPU, and SFRs are reset by using the RESET pin. When a low-level (“L”) signal is applied to the RESET pin

while the supply voltage meets the recommended operating conditions, ports and I/O pins for peripheral functions

are reset. (Refer to Table 5.1 Pin states while RESET pin is held “L”.) Also, the oscillation circuit is reset and the

main clock starts oscillating. CPU and SFRs are reset when the signal applied to the RESET pin changes from “L”

to high-level (“H”) signal, and then the MCU executes a program beginning with the address indicated by the reset

vector. The internal RAM is not reset by hardware reset. When an “L” signal is applied to the RESET pin while

writing data to the internal RAM, the value written to the internal RAM becomes undefined.

Figure 5.1 shows an example of the reset circuit. Figure 5.2 shows a reset sequence. Table 5.1 lists pin states while

the RESET pin is held “L”.

5.1.1

Reset at a Stable Supply Voltage

(1) Apply an “L” signal to the RESET pin.

(2) Input 20 clock cycles or more into the XIN pin.

(3) Apply an “H” signal to the RESET pin.

5.1.2

Power-on Reset

(1) Apply an “L” signal to the RESET pin.

(2) Increase the supply voltage until it meets the recommended operating condition.

(3) Wait for td(P-R) (internal power supply stabilization time) or more to allow the internal power supply to

stabilize.

(4) Inputs 20 clock cycles or more into the XIN pin.

(5) Apply an “H” signal to the RESET pin.

Figure 5.1

Example of Reset Circuit

VCC1

RESET

VCC1

RESET

Recommended

operating voltage

0.2VCC1 or below

Input td(P-R) + 20 clock cycles or more

to the XIN pin

0.2VCC1 or below

NOTE:

1. If operating at VCC1 > VCC2, VCC2 voltage must be lower than VCC1 voltage when powering up and down.

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