M32CSLASH8B datasheet(128/406 Pages) RENESAS

128 / 406 page

Under development

M32C/8B Group

11. Interrupts

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 111 of 385

11.7

INT Interrupt

External input to pins INT0 to INT5 generates the INT0 to INT5 interrupt. INT0 to INT5 interrupts can select

either edge sensitive, which the rising/falling edge triggers an interrupt request, or level sensitive, which an input

signal level to the INTi pin (i = 0 to 5) triggers an interrupt request.

To use INT0 to INT5 interrupts with edge sensitive, set the LVS bit in the INTiIC register to 0 (edge sensitive), and

select a rising edge, falling edge, or both edges using the POL bit in the INTiIC register and the IFSRi bit in the

IFSR register. When the IFSRi bit is set to 1 (both edges), set the corresponding POL bit to 0 (falling edge). When

the selected edge is detected at the INTi pin, the corresponding IR bit becomes 1.

To use INT0 to INT5 interrupts with level sensitive, set the LVS bit to 1 (level sensitive) and select either “L” level

or “H” level using the POL bit. Also, set the IFSRi bit to 0 (one edge). While the selected level is detected at the

INTi pin, the IR bit becomes 1 and remains 1. Therefore, the interrupt requests are generated repeatedly as long as

the selected level is detected at the INTi pin. When the input signal is changed to the inactive level, the IR bit

becomes 0 by the interrupt request acknowledgement or writing a 0 by a program.

Interrupts can be enabled or disabled using bits ILVL2 to ILVL0 in the INTiIC register.

Figure 11.11 shows INTi interrupt setting procedures (i = 0 to 5). Figure 11.12 shows the IFSR register.

M32C/8B 데이터시트(PDF) 128 Page - Renesas Technology Corp