M32CSLASH8B datasheet(257/406 Pages) RENESAS

257 / 406 page

Under development

M32C/8B Group

17. Serial Interfaces

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 240 of 385

17.1.4.3 Clock Phase Setting Function

The clock polarity and clock phase are selected from four combinations of the CKPH and CKPOL bits in the

UiSMR3 register (i = 0 to 4). The master must have the same serial clock polarity and phase as the slaves

involved in the communication. Figure 17.29 shows a transmit and receive operation timing.

Figure 17.29

Transmit and Receive Operation Timing in Special Mode 2

CLKi I/O (CKPOL = 0)

CLKi I/O (CKPOL = 1)

undefined

i=0 to 4

CKPH, DINC: bits in the UiSMR3 register

CKPOL: bit in the UiC0 register

NOTE:

1. P7_0 and P7_1 are N-channel open drain output ports. They must be pulled up externally to output data.

Hi-Z

CLKi I/O (CKPOL = 0)

CLKi I/O (CKPOL = 1)

Hi-Z

(1) When the CKPH = 0 (no clock delay)

(2) When the CKPH = 1 (clock delay)

In master mode

(internal clock)

(DINC = 0)

In slave mode

(external clock)

(DINC = 1)

SSi input pin

TXDi output

SSi input pin

STXDi output (1)

Receive data

input timing

Receive data

input timing

In slave mode

(external clock)

(DINC = 1)

SSi input pin

STXDi

output (1)

Receive data

input timing

In master mode

(internal clock)

(DINC = 0)

SSi input pin

TXDi output

Receive data

input timing

Hi-Z

“H”

“L”

“H”

“L”

“H”

“L”

“H”

“L”

“H”

“L”

“H”

“L”

“H”

“L”

“H”

“L”

“H”

“L”

“H”

“L”

“H”

“L”

“H”

“L”

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