M32CSLASH8B datasheet(274/406 Pages) RENESAS

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Under development

M32C/8B Group

18. A/D Converter

Preliminary specification

Specifications in this manual are tentative and subject to change.

REJ09B0450-0050 Rev.0.50 Oct 31, 2008

Page 257 of 385

Figure 18.6

AD0CON4 Register, AD00 to AD07 Registers

b6 b5 b4

Symbol

AD0CON4

Address

0392h

After Reset

XXXX 00XXb

Function

Bit Symbol

Bit Name

−

(b7-b4)

Reserved bits

A/D0 Control Register 4(1)

MPS10

MPS11

b3 b2

0 0: (Note 4)

0 1: AN_0 to AN_7, AN15_0 to AN15_7

1 0: AN_0 to AN_7, AN0_0 to AN0_7

1 1: AN_0 to AN_7, AN2_0 to AN2_7

Multi-port sweep port

select bits(2, 3)

−

(b1-b0)

Set to 0.

Read as undefined value.

NOTES:

1. If the AD0CON4 register is rewritten during A/D conversion, the conversion result will be incorrect.

2. Do not set bits MPS11 and MPS10 to 01b in the 100-pin package.

3. Bits MPS11 and MPS10 cannot be set to 10b or 11b in memory expansion mode or microprocessor mode.

4. When the MSS bit in the AD0CON3 register is set to 0 (multi-port sweep mode not used), set bits MPS11 and MPS10 to 00b.

When the MSS bit is set to 1 (multi-port sweep mode used), set bits MPS11 and MPS10 to other than 00b.

Reserved bits

Set to 0.

Read as undefined value.

b15

A/D0 Register i(1, 2, 3, 4) (i = 0 to 7)

Symbol

AD00

AD01 to AD03

AD04 to AD06

AD07

Address

0381h - 0380h

0383h - 0382h, 0385h - 0384h, 0387h - 0386h

0389h - 0388h, 038Bh - 038Ah, 038Dh - 038Ch

038Fh - 038Eh

After Reset

00000000 XXXXXXXXb

Function

NOTES:

1. When the AD0i register is read by a program in DMAC operating mode, the conversion result is incorrect.

2. If the next A/D conversion result is stored before reading the previous result in the AD0i register, the result will be incorrect.

3. Only AD00 register is enabled in DMAC operating mode. The contents of other registers are undefined.

4. When using both DMAC operating mode and 10-bit mode, select a 16-bit transfer for DMAC.

In 10-bit mode: 2 high-order bits of A/D conversion result

In 8-bit mode: Read as 0.

8 low-order bits of A/D conversion result

Reserved bits. Read as 0.

0 0

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