H8S2245 datasheet(444/818 Pages) RENESAS

444 / 818 page

Section 11 Watchdog Timer

Rev.3.00 Mar. 26, 2007 Page 402 of 772

REJ09B0355-0300

11.5.3

Switching between Watchdog Timer Mode and Interval Timer Mode

If the mode is switched from watchdog timer to interval timer, or vice versa, while the WDT is

operating, errors could occur in the incrementation. Software must stop the watchdog timer (by

clearing the TME bit to 0) before switching the mode.

11.5.4

System Reset by

WDTOVF

WDTOVF Signal

If the

WDTOVF output signal is input to the RES pin of the H8S/2245 Group, the H8S/2245

Group will not be initialized correctly. Make sure that the

WDTOVF signal is not input logically

to the

RES pin. To reset the entire system by means of the WDTOVF signal, use the circuit shown

in figure 11.9.

Reset input

Reset signal to entire system

H8S/2245

RES

WDTOVF

Figure 11.9 Circuit for System Reset by

WDTOVF

WDTOVF Signal (Example)

11.5.5

Internal Reset in Watchdog Timer Mode

The H8S/2245 Group is not reset internally if TCNT overflows while the RSTE bit is cleared to 0

during watchdog timer operation, but TCNT and TSCR of the WDT are reset.

TCNT, TCSR, and RSTCR cannot be written to while the

WDTOVF signal is low. Also note that

a read of the WOVF flag is not recognized during this period. To clear the WOVF flag, therefore,

read TCSR after the

WDTOVF signal goes high, then write 0 to the WOVF flag.

11.5.6

OVF Flag Clearing in Interval Timer Mode

When the OVF flag setting conflicts with the OVF flag reading in interval timer mode, writing 0

to the OVF bit may not clear the flag even though the OVF bit has been read while it is 1. If there

is a possibility that the OVF flag setting and reading will conflict, such as when the OVF flag is

polled with the interval timer interrupt disabled, read the OVF bit while it is 1 at least twice before

writing 0 to the OVF bit to clear the flag.

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