H8S2245 datasheet(574/818 Pages) RENESAS

574 / 818 page

Section 16 ROM

Rev.3.00 Mar. 26, 2007 Page 532 of 772

REJ09B0355-0300

16.3

Operation

The on-chip ROM is connected to the CPU by a 16-bit data bus, and both byte and word data can

be accessed in one state. Even addresses are connected to the upper 8 bits, and odd addresses to

the lower 8 bits. Word data must start at an even address.

The on-chip ROM is enabled and disabled by setting the mode pins (MD

2, MD1, and MD0) and bit

EAE in BCRL. These settings are shown in table 16.2.

In the H8S/2246, H8S/2245, H8S/2244, and H8S/2243 normal mode, a maximum of 56 kbytes of

ROM can be used.

Table 16.2

Operating Modes and ROM Area

Mode Pin Setting

BCRL

On-Chip ROM

Operating Mode

EAE

H8S/2246 and

H8S/2245

H8S/2244 and

H8S/2243

H8S/2242 and

H8S/2241

Mode 1

Normal expanded

mode with on-chip

ROM disabled

—

Disabled

Mode 2

Normal expanded

mode with on-chip

ROM enabled

—

Enabled

(56 kbytes)

Enabled

(56 kbytes)

Enabled

(32 kbytes)

Mode 3

Normal single-chip

mode

Mode 4

Advanced expanded

mode with on-chip

ROM disabled

—

Disabled

Mode 5

Advanced expanded

mode with on-chip

ROM disabled

Mode 6

Enabled

(128 kbytes)

Enabled

(64 kbytes)

Enabled

(32 kbytes)

Advanced expanded

mode with on-chip

ROM enabled

Enabled

(64 kbytes)

Mode 7

Advanced single-chip

mode

Enabled

(128 kbytes)

Enabled

(64 kbytes)

In H8S/2246 and H8S/2245 modes 6 and 7, the on-chip ROM available after a power-on reset is

the 64-kbyte area comprising addresses H'000000 to H'00FFFF.

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