H8S2245 datasheet(173/818 Pages) RENESAS

173 / 818 page

Section 6 Bus Controller

Rev.3.00 Mar. 26, 2007 Page 131 of 772

REJ09B0355-0300

Section 6 Bus Controller

6.1

Overview

The H8S/2245 Group has a built-in bus controller (BSC) that manages the external address space

divided into eight areas. The bus specifications, such as bus width and number of access states,

can be set independently for each area, enabling multiple memories to be connected easily.

The bus controller also has a bus arbitration function, and controls the operation of the internal bus

masters: the CPU and the data transfer controller (DTC).

6.1.1

Features

The features of the bus controller are listed below.

• Manages external address space in area units

 In advanced mode, manages the external space as 8 areas of 128-kbytes/2-Mbytes

 In normal mode, manages the external space as a single area

 Bus specifications can be set independently for each area

 Burst ROM interface can be set

• Basic bus interface

 Chip select (CS0 to CS3) can be output for areas 0 to 3

 8-bit access or 16-bit access can be selected for each area

 2-state access or 3-state access can be selected for each area

 Program wait states can be inserted for each area

• Burst ROM interface

 Burst ROM interface can be set for area 0

 1-state or 2-state burst access can be selected

• Idle cycle insertion

 An idle cycle can be inserted in case of an external read cycle between different areas

 An idle cycle can be inserted in case of an external write cycle immediately after an

external read cycle

• Bus arbitration function

 Includes a bus arbiter that arbitrates bus mastership among the CPU, and DTC

• Other features

 External bus release function

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