H8S2245 datasheet(232/818 Pages) RENESAS

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Section 7 Data Transfer Controller

Rev.3.00 Mar. 26, 2007 Page 190 of 772

REJ09B0355-0300

DTCER clearance. The activation source flag, in the case of RXI0, for example, is the RDRF flag

of SCI0. As there are a number of activation sources, the activation source flag is not cleared with

the last byte (or word) transfer. Take appropriate measures at each interrupt.

Table 7.3

Activation Source and DTCER Clearance

Activation Source

When the DISEL Bit Is 0 and

the Specified Number of

Transfers Have Not Ended

When the DISEL Bit Is 1, or when

the Specified Number of Transfers

Have Ended

Software activation

The SWDTE bit is cleared to 0

The SWDTE bit remains set to 1

An interrupt request is issued to the CPU

Interrupt activation

The corresponding DTCER bit

remains set to 1

The activation source flag is

cleared to 0

The corresponding DTCER bit is cleared

to 0

The activation source flag remains set to 1

A request is issued to the CPU for the

activation source interrupt

Figure 7.3 shows a block diagram of activation source control. For details see section 5, Interrupt

Controller.

On-chip

supporting

module

IRQ interrupt

DTVECR

Interrupt controller

CPU

DTC

DTCER

Clear

controller

Select

Interrupt

request

Source flag cleared

Clear

Clear request

Interrupt mask

Figure 7.3 Block Diagram of DTC Activation Source Control

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