HD64F2149YV datasheet(347/1075 Pages) RENESAS

347 / 1075 page

Section 11 16-Bit Free-Running Timer

Rev. 3.00 Jan 18, 2006 page 319 of 1044

REJ09B0280-0300

Bit 7

ICFA

Description

[Clearing condition]

Read ICFA when ICFA = 1, then write 0 in ICFA

(Initial value)

[Setting condition]

When an input capture signal causes the FRC value to be transferred to ICRA

Bit 6—Input Capture Flag B (ICFB): This status flag indicates that the FRC value has been

transferred to ICRB by means of an input capture signal. When BUFEB = 1, ICFB indicates that

the old ICRB value has been moved into ICRD and the new FRC value has been transferred to

ICRB.

ICFB must be cleared by software. It is set by hardware, however, and cannot be set by software.

Bit 6

ICFB

Description

[Clearing condition]

Read ICFB when ICFB = 1, then write 0 in ICFB

(Initial value)

[Setting condition]

When an input capture signal causes the FRC value to be transferred to ICRB

Bit 5—Input Capture Flag C (ICFC): This status flag indicates that the FRC value has been

transferred to ICRC by means of an input capture signal. When BUFEA = 1, on occurrence of the

signal transition in FTIC (input capture signal) specified by the IEDGC bit, ICFC is set but data is

not transferred to ICRC. Therefore, in buffer operation, ICFC can be used as an external interrupt

signal (by setting the ICICE bit to 1).

ICFC must be cleared by software. It is set by hardware, however, and cannot be set by software.

Bit 5

ICFC

Description

[Clearing condition]

Read ICFC when ICFC = 1, then write 0 in ICFC

(Initial value)

[Setting condition]

When an input capture signal is received

HD64F2149YV 데이터시트(PDF) 347 Page - Renesas Technology Corp