HD64F2149YV datasheet(8/1075 Pages) RENESAS

8 / 1075 page

Rev. 3.00 Jan 18, 2006 page viii of xxviii

Item

Page

Revision (See Manual for Details)

16.4 Usage Notes

551 to

558

Description added

• Notes on WAIT Function of the I

2C Bus Interface

• Notes on ICDR Reads and ICCR Access in Slave Transmit

Mode

• Notes on TRS Bit Setting in Slave Mode

• Notes on Arbitration Lost in I

2C Bus Interface

• Notes on Interrupt Occurrence after ACKB Reception

• Notes on TRS Bit Setting and ICDR Register Access in I

Bus Interface

20.2.3 A/D Control

668

Description amended

Bits 5 to 0 (Before) Reserved: Should always be written with 1.

→ (After) Reserved: Always be read as1, and cannot be

modified.

20.4.3 Input

Sampling and A/D

Conversion Time

Figure 20.5 A/D

Conversion Timing

676

Figure 20.5 amended

(1)

(2)

Address

Write signal

24.2.2 Low-Power

Control Register

(LPWRCR)

753

Bit figure amended

DTON

R/W

LSON

R/W

NESEL

R/W

EXCLE

R/W

—

Bit

Initial value

Read/Write

24.5.1 Module Stop

Mode

Table 24.4 MSTP

Bits and

Corresponding On-

Chip Supporting

Modules

760

Module of MSTPCRL register amended

MSTO0 (Before) Host Interface (HIF: LPC), keyboard buffer

controller (PS2)

→ (After) Host Interface (HIF: LPC), wakeup

event interrupt mask register B (WUEMRB)

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