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HD64F2149YV 데이터시트(PDF) 369 Page - Renesas Technology Corp

부품명 HD64F2149YV
상세설명  Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series
PDF  1075 Pages
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제조업체  RENESAS [Renesas Technology Corp]
홈페이지  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

HD64F2149YV 데이터시트(HTML) 369 Page - Renesas Technology Corp

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Section 11 16-Bit Free-Running Timer
Rev. 3.00 Jan 18, 2006 page 341 of 1044
REJ09B0280-0300
Contention between OCR Write and Compare-Match: If a compare-match occurs during the
state after an OCRA or OCRB write cycle, the write takes priority and the compare-match signal
is inhibited.
Figure 11.20 shows this type of contention.
If automatic addition of OCRAR/OCRAF to OCRA is selected, and a compare-match occurs in
the cycle following the OCRA, OCRAR and OCRAF write cycle, the OCRA, OCRAR and
OCRAF write takes priority and the compare-match signal is inhibited. Consequently, the result of
the automatic addition is not written to OCRA.
Figure 11.21 shows this timing
T1
T2
OCRA or OCRB write cycle
Address
Internal write signal
φ
FRC
OCR
N
M
Write data
OCR address
N
N + 1
Compare-match
signal
Prohibited
Figure 11.20 Contention between OCR Write and Compare-Match
(When Automatic Addition Function Is Not Used)



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