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HD64F2149YV 데이터시트(PDF) 385 Page - Renesas Technology Corp |
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HD64F2149YV 데이터시트(HTML) 385 Page - Renesas Technology Corp |
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385 / 1075 page ![]() Section 12 8-Bit Timers Rev. 3.00 Jan 18, 2006 page 357 of 1044 REJ09B0280-0300 12.2.5 Timer Control/Status Register (TCSR) 7 CMFB 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 4 ICIE 0 R/W 3 OS3 0 R/W 0 OS0 0 R/W 2 OS2 0 R/W 1 OS1 0 R/W Bit Initial value Read/Write Note: * Only 0 can be written in bits 7 to 5, and in bit 4 in TCSRX, to clear these flags. TCSRY 7 CMFB 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 4 ICF 0 R/(W)* 3 OS3 0 R/W 0 OS0 0 R/W 2 OS2 0 R/W 1 OS1 0 R/W Bit Initial value Read/Write TCSRX 7 CMFB 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 4 — 1 — 3 OS3 0 R/W 0 OS0 0 R/W 2 OS2 0 R/W 1 OS1 0 R/W Bit Initial value Read/Write TCSR1 7 CMFB 0 R/(W)* 6 CMFA 0 R/(W)* 5 OVF 0 R/(W)* 4 ADTE 0 R/W 3 OS3 0 R/W 0 OS0 0 R/W 2 OS2 0 R/W 1 OS1 0 R/W Bit Initial value Read/Write TCSR0 TCSR is an 8-bit register that indicates compare-match and overflow statuses (and input capture status in TMRX only), and controls compare-match output. TCSR0, TCSRX, and TCSRY are initialized to H'00, and TCSR1 is initialized to H'10, by a reset and in hardware standby mode. |
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