HD64F2149YV datasheet(530/1075 Pages) RENESAS

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Section 16 I

2C Bus Interface

Rev. 3.00 Jan 18, 2006 page 502 of 1044

REJ09B0280-0300

DDCSWR

Bit 6

SAR

Bit 0

SARX

Bit 0

FSX

Operating Mode

2C bus format

• SAR and SARX slave addresses recognized

2C bus format

(Initial value)

• SAR slave address recognized

• SARX slave address ignored

2C bus format

• SAR slave address ignored

• SARX slave address recognized

Synchronous serial format

• SAR and SARX slave addresses ignored

Formatless mode (start/stop conditions not detected)

• Acknowledge bit used

Formatless mode* (start/stop conditions not detected)

• No acknowledge bit

Note:

Do not set this mode when automatic switching to the I

2C bus format is performed by

means of the DDCSWR setting.

16.2.3

Second Slave Address Register (SARX)

Bit

Initial value

Read/Write

SVAX6

R/W

SVAX5

R/W

SVAX4

R/W

SVAX3

R/W

SVAX2

R/W

FSX

R/W

SVAX1

R/W

SVAX0

R/W

SARX is an 8-bit readable/writable register that stores the second slave address and selects the

communication format. When the chip is in slave mode (and the addressing format is selected), if

the upper 7 bits of SARX match the upper 7 bits of the first frame received after a start condition,

the chip operates as the slave device specified by the master device. SARX is assigned to the same

address as ICDR, and can be written and read only when the ICE bit is cleared to 0 in ICCR.

SARX is initialized to H'01 by a reset and in hardware standby mode.

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