| 전자부품 데이터시트 검색엔진 |
|
HD64F2149YV 데이터시트(PDF) 538 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
HD64F2149YV 데이터시트(HTML) 538 Page - Renesas Technology Corp |
|
538 / 1075 page ![]() Section 16 I 2C Bus Interface Rev. 3.00 Jan 18, 2006 page 510 of 1044 REJ09B0280-0300 Bit 3 ACKE Description 0 The value of the acknowledge bit is ignored, and continuous transfer is performed (Initial value) 1 If the acknowledge bit is 1, continuous transfer is interrupted Bit 2—Bus Busy (BBSY): The BBSY flag can be read to check whether the I 2C bus (SCL, SDA) is busy or free. In master mode, this bit is also used to issue start and stop conditions. A high-to-low transition of SDA while SCL is high is recognized as a start condition, setting BBSY to 1. A low-to-high transition of SDA while SCL is high is recognized as a stop condition, clearing BBSY to 0. To issue a start condition, use a MOV instruction to write 1 in BBSY and 0 in SCP. A retransmit start condition is issued in the same way. To issue a stop condition, use a MOV instruction to write 0 in BBSY and 0 in SCP. It is not possible to write to BBSY in slave mode; the I 2C bus interface must be set to master transmit mode before issuing a start condition. MST and TRS should both be set to 1 before writing 1 in BBSY and 0 in SCP. Bit 2 BBSY Description 0 Bus is free (Initial value) [Clearing condition] When a stop condition is detected 1Bus is busy [Setting condition] When a start condition is detected Bit 1—I 2C Bus Interface Interrupt Request Flag (IRIC): Indicates that the I2C bus interface has issued an interrupt request to the CPU. IRIC is set to 1 at the end of a data transfer, when a slave address or general call address is detected in slave receive mode, when bus arbitration is lost in master transmit mode, and when a stop condition is detected. IRIC is set at different times depending on the FS bit in SAR and the WAIT bit in ICMR. See section 16.3.6, IRIC Setting Timing and SCL Control. The conditions under which IRIC is set also differ depending on the setting of the ACKE bit in ICCR. IRIC is cleared by reading IRIC after it has been set to 1, then writing 0 in IRIC. |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |