HD64F2149YV datasheet(543/1075 Pages) RENESAS

543 / 1075 page

Section 16 I

2C Bus Interface

Rev. 3.00 Jan 18, 2006 page 515 of 1044

REJ09B0280-0300

IRTR flag setting is performed when the TDRE or RDRF flag is set to 1. IRTR is cleared by

reading IRTR after it has been set to 1, then writing 0 in IRTR. IRTR is also cleared automatically

when the IRIC flag is cleared to 0.

Bit 5

IRTR

Description

Waiting for transfer, or transfer in progress

(Initial value)

[Clearing conditions]

1. When 0 is written in IRTR after reading IRTR = 1

2. When the IRIC flag is cleared to 0

Continuous transfer state

[Setting condition]

• In I2C bus interface slave mode

When the TDRE or RDRF flag is set to 1 when AASX = 1

• In other modes

When the TDRE or RDRF flag is set to 1

Bit 4—Second Slave Address Recognition Flag (AASX): In I

2C bus format slave receive mode,

this flag is set to 1 if the first frame following a start condition matches bits SVAX6 to SVAX0 in

SARX.

AASX is cleared by reading AASX after it has been set to 1, then writing 0 in AASX. AASX is

also cleared automatically when a start condition is detected.

Bit 4

AASX

Description

Second slave address not recognized

(Initial value)

[Clearing conditions]

1. When 0 is written in AASX after reading AASX = 1

2. When a start condition is detected

3. In master mode

Second slave address recognized

[Setting condition]

When the second slave address is detected in slave receive mode while FSX = 0

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