HD64F2149YV datasheet(572/1075 Pages) RENESAS

572 / 1075 page

Section 16 I

2C Bus Interface

Rev. 3.00 Jan 18, 2006 page 544 of 1044

REJ09B0280-0300

Notes on Initialization:

• Interrupt flags and interrupt sources are not cleared, and so flag clearing measures must be

taken as necessary.

• Basically, other register flags are not cleared either, and so flag clearing measures must be

taken as necessary.

• When initialization is executed by the DDCSWR register, the write data for bits CLR3 to

CLR0 is not retained. To perform IIC clearance, bits CLR3 to CLR0 must be written to

simultaneously using an MOV instruction. Do not use a bit manipulation instruction such as

BCLR. Similarly, when clearing is required again, all the bits must be written to

simultaneously in accordance with the setting.

• If a flag clearing setting is made during transmission/reception, the IIC module will stop

transmitting/receiving at that point and the SCL and SDA pins will be released. When

transmission/reception is started again, register initialization, etc., must be carried out as

necessary to enable correct communication as a system.

The value of the BBSY bit cannot be modified directly by this module clear function, but since the

stop condition pin waveform is generated according to the state and release timing of the SCL and

SDA pins, the BBSY bit may be cleared as a result. Similarly, state switching of other bits and

flags may also have an effect.

To prevent problems caused by these factors, the following procedure should be used when

initializing the IIC state.

1. Execute initialization of the internal state according to the setting of bits CLR3 to CLR0 or

ICE bit clearing.

2. Execute a stop condition issuance instruction (write 0 to BBSY and SCP) to clear the BBSY

bit to 0, and wait for two transfer rate clock cycles.

3. Re-execute initialization of the internal state according to the setting of bits CLR3 to CLR0 or

ICE bit clearing.

4. Initialize (re-set) the IIC registers.

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