HD64F2149YV datasheet(579/1075 Pages) RENESAS

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Section 16 I

2C Bus Interface

Rev. 3.00 Jan 18, 2006 page 551 of 1044

REJ09B0280-0300

• Notes on WAIT Function

 Conditions to cause this phenomenon

When both of the following conditions are satisfied, the clock pulse of the 9th clock could

be outputted continuously in master mode using the WAIT function due to the failure of

the WAIT insertion after the 8th clock fall.

(1) Setting the WAIT bit of the ICMR register to 1 and operating WAIT, in master mode

(2) If the IRIC bit of interrupt flag is cleared from 1 to 0 between the fall of the 7th clock

and the fall of the 8th clock.

 Error phenomenon

Normally, WAIT State will be cancelled by clearing the IRIC flag bit from 1 to 0 after the

fall of the 8th clock in WAIT State. In this case, if the IRIC flag bit is cleared between the

7th clock fall and the 8th clock fall, the IRIC flag clear- data will be retained internally.

Therefore, the WAIT State will be cancelled right after WAIT insertion on 8th clock fall.

 Restrictions

Please clear the IRIC flag before the rise of the 7th clock (the counter value of BC2

through BC0 should be 2 or greater), after the IRIC flag is set to 1 on the rise of the 9th

clock.

If the IRIC flag-clear is delayed due to the interrupt or other processes and the value of BC

counter is turned to 1 or 0, please confirm the SCL pins are in L’ state after the counter

value of BC2 through BC0 is turned to 0, and clear the IRIC flag. (See figure 16.21.)

SCL

BC2–BC0

Transmit/receive data

ASD

IRIC flag clear unavailable

IRIC flag clear available

IRIC

(operation

example)

SCL =

‘L’ confirm

IRIC clear

When BC2-0

≥ 2

IRIC clear

Transmit/receive

data

Figure 16.21 IRIC Flag Clear Timing on WAIT Operation

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