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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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HD64F2149YV 데이터시트(PDF) 597 Page - Renesas Technology Corp |
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HD64F2149YV 데이터시트(HTML) 597 Page - Renesas Technology Corp |
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597 / 1075 page  Section 17 Keyboard Buffer Controller Rev. 3.00 Jan 18, 2006 page 569 of 1044 REJ09B0280-0300 12 3 KCLK (pin state) KD (pin state) KCLK (input) KCLK (output) KB7 to KB0 PER KBS KBF Start bit Parity bit Stop bit Receive processing/ error handling Automatic I/O inhibit Previous data Receive data Flag cleared 9 10 11 7 01 KB0 KB1 [1] [2] [3] [4] [5] [6] Figure 17.4 Receive Timing 17.3.2 Transmit Operation In a transmit operation, KCLK (clock) is an output on the keyboard side, and KD (data) is an output on the chip (system) side. KD outputs a start bit, 8 data bits (LSB-first), an odd parity bit, and a stop bit, in that order. The KD value is valid when KCLK is high. A sample transmit processing flowchart is shown in figure 17.5, and the transmit timing in figure 17.6. |
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