 |
전자부품 데이터시트 검색엔진 |
|
|
전자부품 데이터시트 검색엔진 |
|
HD64F2149YV 데이터시트(PDF) 616 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
HD64F2149YV 데이터시트(HTML) 616 Page - Renesas Technology Corp |
|
|
616 / 1075 page  Section 18A Host Interface X-Bus Interface (XBS) Rev. 3.00 Jan 18, 2006 page 588 of 1044 REJ09B0280-0300 18A.2.3 Host Interface Control Register (HICR) • HICR Bit Initial value Slave Read/Write Host Read/Write 7 — 1 — — 6 — 1 — — 5 — 1 — — 4 — 1 — — 3 — 1 — — 0 FGA20E 0 R/W — 2 IBFIE2 0 R/W — 1 IBFIE1 0 R/W — • HICR2 Bit Initial value Slave Read/Write Host Read/Write 7 — 1 — — 6 — 1 — — 5 — 1 — — 4 — 1 — — 3 — 1 — — 0 — 0 — — 2 IBFIE4 0 R/W — 1 IBFIE3 0 R/W — HICR is an 8-bit readable/writable register which controls host interface channel 1 and 2 interrupts and the fast A20 gate function. HICR2 is an 8-bit readable/writable register which controls host interface channel 3 and 4 interrupts. HICR and HICR2 are initialized to H'F8 by a reset and in hardware standby mode. Bits 7 to 3—Reserved: These bits cannot be modified and are always read as 1. HICR Bits 2 and 1—Input Data Register Full Interrupt Enable 2 and 1 (IBFIE2, IBFIE1) HICR2 Bits 2 and 1—Input Data Register Full Interrupt Enable 4 and 3 (IBFIE4, IBFIE3) These bits enable or disable the IBF1 to IBF4 interrupts to the internal CPU. |
|
링크 URL |
| ALLDATASHEET 가 귀하에 도움이 되셨나요? [ DONATE ] |
Alldatasheet는? | 광고문의 | 운영자에게 연락하기 | 개인정보취급방침 | 링크 투 데이터시트 | 링크교환 | 제조사별 검색 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Korean ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
