HD64F2149YV datasheet(650/1075 Pages) RENESAS

650 / 1075 page

Section 18B Host Interface LPC Interface (LPC)

Rev. 3.00 Jan 18, 2006 page 622 of 1044

REJ09B0280-0300

18B.2.7 Two-Way Data Registers (TWR0 to TWR15)

• TWR0MW

Bit

543

210

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Initial value

—

———

Slave Read/Write

Host Read/Write

WWW

• TWR0SW

Bit

543

210

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Initial value

—

———

Slave Read/Write

Host Read/Write

RRR

• TWR1 to TWR15

Bit

543

210

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Initial value

—

———

Slave Read/Write

R/W

Host Read/Write

R/W

TWR0 to TWR15 are sixteen 8-bit readable/writable registers to both the slave processor and the

host processor. In TWR0, however, two registers (TWR0MW and TWR0SW) are allocated to the

same address for both the host address and the slave address. TWR0MW is a write-only register to

the host processor, and a read-only register to the slave processor, while TWR0SW is a write-only

slave processors begin a write, after the respective TWR0 registers have been written to, access

right arbitration for simultaneous access is performed by checking the status flags to see if those

writes were valid. For the registers selected from the host according to the I/O address, see section

18B.2.4, LPC Channel 3 Address Register (LADR3).

Data transferred in an LPC I/O write cycle is written to the selected register; in an LPC I/O read

cycle, the data in the selected register is transferred to the host.

HD64F2149YV 데이터시트(PDF) 650 Page - Renesas Technology Corp

HD64F2149YV 데이터시트(HTML) 650 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL