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HD64F2149YV 데이터시트(PDF) 808 Page - Renesas Technology Corp |
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HD64F2149YV 데이터시트(HTML) 808 Page - Renesas Technology Corp |
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808 / 1075 page ![]() Section 25 Electrical Characteristics Rev. 3.00 Jan 18, 2006 page 780 of 1044 REJ09B0280-0300 25.3.1 Clock Timing Table 25.5 shows the clock timing. The clock timing specified here covers clock ( φ) output and clock pulse generator (crystal) and external clock input (EXTAL pin) oscillation settling times. For details of external clock input (EXTAL pin and EXCL pin) timing, see section 23, Clock Pulse Generator. Table 25.5 Clock Timing Condition: V CC = 2.7 V to 3.6 V, VCCB = 2.7 V to 5.5 V, VSS = 0 V, φ = 2 MHz to maximum operating frequency, T a = –20 to +75°C Condition 10 MHz Item Symbol Min Max Unit Test Conditions Clock cycle time t cyc 100 500 ns Figure 25.4 Clock high pulse width t CH 30 — ns Clock low pulse width t CL 30 — ns Clock rise time t Cr — 20 ns Clock fall time t Cf — 20 ns Oscillation settling time at reset (crystal) t OSC1 20 — ms Oscillation settling time in software standby (crystal) t OSC2 8 — ms External clock output stabilization delay time t DEXT 500 — µs Figure 25.5 Figure 25.6 tCH tcyc tCf tCL tCr φ Figure 25.4 System Clock Timing |
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