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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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HD64F2149YV 데이터시트(PDF) 820 Page - Renesas Technology Corp |
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HD64F2149YV 데이터시트(HTML) 820 Page - Renesas Technology Corp |
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820 / 1075 page  Section 25 Electrical Characteristics Rev. 3.00 Jan 18, 2006 page 792 of 1044 REJ09B0280-0300 Condition 10 MHz Item Symbol Min Max Unit Test Conditions SCI Asynchronous t Scyc 4 — t cyc Figure 25.21 Input clock cycle Synchronous 6 — Input clock pulse width t SCKW 0.4 0.6 t Scyc Input clock rise time t SCKr — 1.5 t cyc Input clock fall time t SCKf — 1.5 Transmit data delay time (synchronous) t TXD — 100 ns Receive data setup time (synchronous) t RXS 100 — ns Figure 25.22 Receive data hold time (synchronous) t RXH 100 — ns A/D converter Trigger input setup time t TRGS 50 — ns Figure 25.23 WDT RESO output delay time t RESD — 200 ns Figure 25.24 RESO output pulse width t RESOW 132 — t cyc Note: * Only supporting modules that can be used in subclock operation φ Ports 1 to 9, A to G (read) T2 T1 tPWD tPRH tPRS Ports 1 to 6, 8, 9, A to G (write) Figure 25.14 I/O Port Input/Output Timing |
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