HD64F2149YV datasheet(989/1075 Pages) RENESAS

부품명	HD64F2149YV

상세설명	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

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Appendix B Internal I/O Registers

Rev. 3.00 Jan 18, 2006 page 961 of 1044

REJ09B0280-0300

STCR—Serial Timer Control Register

H'FFC3

System

IICS

R/W

IICX1

R/W

IICX0

R/W

IICE

R/W

FLSHE

R/W

ICKS0

R/W

—

R/W

ICKS1

R/W

Bit

Initial value

Read/Write

Notes: 1.

Internal Clock Source

Select*1

Reserved bit

Flash memory control register enable

Flash memory control register not selected

Flash memory control register selected

I2C master enable

CPU access to SCI0, SCI1, and SCI2 control

registers is enabled

CPU access to I2C bus interface data, PWMX and

control registers is enabled

PA7 to PA4 are normal I/O pins

PA7 to PA4 are I/O pins with bus driving capability

I2C transfer select 1 and 0*2

I2C extra buffer select

Used for 8-bit timer input clock selection. For details, see section 12.2.4, Timer

Control Register (TCR).

Used for I2C bus interface transfer clock selection. For details, see section 16.2.4,

I2C Bus Mode Register (ICMR).

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