HD64F2149YV datasheet(126/1075 Pages) RENESAS

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HD64F2149YV 데이터시트(PDF) 126 Page - Renesas Technology Corp

부품명	HD64F2149YV

상세설명	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

PDF	1075 Pages

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제조업체	RENESAS [Renesas Technology Corp]

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126 / 1075 page

Section 4 Exception Handling

Rev. 3.00 Jan 18, 2006 page 98 of 1044

REJ09B0280-0300

4.4

Trap Instruction

Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction

exception handling can be executed at all times in the program execution state.

The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector

number from 0 to 3, as specified in the instruction code.

Table 4.3 shows the status of CCR and EXR after execution of trap instruction exception handling.

Table 4.3

Status of CCR and EXR after Trap Instruction Exception Handling

CCR

EXR

Interrupt Control Mode

I2 to I0

—

Legend:

1: Set to 1

0: Cleared to 0

—: Retains value prior to execution.

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