HD64F2149YV datasheet(213/1075 Pages) RENESAS

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HD64F2149YV 데이터시트(PDF) 213 Page - Renesas Technology Corp

부품명	HD64F2149YV

상세설명	Renesas 16-Bit Single-Chip Microcomputer H8S Family/H8S/2100 Series

PDF	1075 Pages

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제조업체	RENESAS [Renesas Technology Corp]

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213 / 1075 page

Section 7 Data Transfer Controller

Rev. 3.00 Jan 18, 2006 page 185 of 1044

REJ09B0280-0300

7.3.5

Normal Mode

In normal mode, one operation transfers one byte or one word of data.

From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a

CPU interrupt can be requested.

Table 7.5 lists the register information in normal mode and figure 7.6 shows memory mapping in

normal mode.

Table 7.5

Name

Abbreviation

Function

DTC source address register

SAR

Transfer source address

DTC destination address register

DAR

Transfer destination address

DTC transfer count register A

CRA

Transfer count

DTC transfer count register B

CRB

Not used

Transfer

SAR

DAR

Figure 7.6 Memory Mapping in Normal Mode

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