HD64F2149YV datasheet(326/1075 Pages) RENESAS

326 / 1075 page

Section 10 14-Bit PWM Timer

Rev. 3.00 Jan 18, 2006 page 298 of 1044

REJ09B0280-0300

Bit 1—Carrier Frequency Select (CFS)

Bit 1

CFS

Description

Base cycle = resolution (T)

× 64

DADR range = H'0401 to H'FFFD

Base cycle = resolution (T)

× 256

DADR range = H'0103 to H'FFFF

(Initial value)

DADRA Bit 0—Reserved: This bit cannot be modified and is always read as 1.

DADRB Bit 0—Register Select (REGS): DADRA and DACR, and DADRB and DACNT, are

located at the same addresses. The REGS bit specifies which registers can be accessed. The REGS

bit can be accessed regardless of whether DADRB or DACNT is selected.

Bit 0

REGS

Description

DADRA and DADRB can be accessed

DACR and DACNT can be accessed

(Initial value)

10.2.3

PWM (D/A) Control Register (DACR)

TEST

R/W

PWME

R/W

—

OEB

R/W

CKS

R/W

OEA

R/W

Bit

Initial value

Read/Write

DACR is an 8-bit readable/writable register that selects test mode, enables the PWM outputs, and

selects the output phase and operating speed.

DACR is initialized to H'30 by a reset, and in the standby modes, watch mode, subactive mode,

subsleep mode, and module stop mode.

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