H8SXSLASH1663 datasheet(723/1158 Pages) RENESAS

723 / 1158 page

Section 15 Serial Communication Interface (SCI, IrDA, CRC)

Rev.1.00 Jun. 07, 2006 Page 671 of 1102

REJ09B0294-0100

Bit

Bit Name

Initial

Value

R/W

Description

CKE1

CKE0

R/W

Clock Enable 1, 0*

These bits control the clock output from the SCK pin. In

GSM mode, clock output can be dynamically switched.

For details, see section 15.7.8, Clock Output Control.

• When GM in SMR = 0

00: Output disabled (SCK pin functions as I/O port.) *

01: Clock output

1X: Reserved

• When GM in SMR = 1

00: Output fixed low

01: Clock output

10: Output fixed high

11: Clock output

Note:

No SCK pins exist in SCI_5 and SCI_6.

15.3.7

Serial Status Register (SSR)

SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. TDRE,

RDRF, ORER, PER, and FER can only be cleared. Some bits in SSR have different functions in

normal mode and smart card interface mode.

• When SMIF in SCMR = 0

Bit

Bit Name

Initial Value

R/W

TDRE

R/(W)*

RDRF

R/(W)*

ORER

R/(W)*

FRE

R/(W)*

PER

R/(W)*

TEND

MPB

MPBT

R/W

Note: * Only 0 can be written, to clear the flag.

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