H8SXSLASH1663 datasheet(816/1158 Pages) RENESAS

816 / 1158 page

Section 16 USB Function Module (USB)

Rev.1.00 Jun. 07, 2006 Page 764 of 1102

REJ09B0294-0100

Bit

Bit Name

Initial

Value

R/W

Description

SSRSME

R/W

Resume Detection for Software Standby Cancel

For the details of the operation, see section 16.5.3,

Suspend and Resume Operations.

6, 5



All 0

R/W

Reserved

These bits are always read as 0. The write value

should always be 0.

SURSE

R/W

Suspend/Resume Detection

For the details of the operation, see section 16.5.3,

Suspend and Resume Operations.

CFDN

R/W

End Point Information Load End



Reserved

This bit is always read as 0. The write value should

always be 0.

SETCE

R/W

Set_Configuration Command Detection

SETIE

R/W

Set_Interface Command Detection

16.3.10

EP0i Data Register (EPDR0i)

EPDR0i is an 8-byte transmit FIFO buffer for endpoint 0. EPDR0i holds one packet of transmit

data for control-in. Transmit data is fixed by writing one packet of data and setting EP0iPKTE in

the trigger register. When an ACK handshake is returned from the host after the data has been

transmitted, EP0iTS in interrupt flag register 0 is set. This FIFO buffer can be initialized by means

of EP0iCLR in the FCLR register.

Bit

Bit Name

Initial Value

R/W

Undefined

Bit

Bit Name

Initial

Value

R/W

Description

7 to 0

D7 to D0

Undefined W

Data register for control-in transfer

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