H8SXSLASH1663 datasheet(964/1158 Pages) RENESAS

부품명	H8SX/1663

상세설명	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

PDF	1158 Pages

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제조업체	RENESAS [Renesas Technology Corp]

홈페이지	http://www.renesas.com

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964 / 1158 page

Section 21 Flash Memory (0.18-

µm F-ZTAT Version)

Rev.1.00 Jun. 07, 2006 Page 912 of 1102

REJ09B0294-0100

(1) On-Chip RAM Address Map when Programming/Erasing is Executed

Parts of the procedure program that is made by the user, like download request,

programming/erasing procedure, and decision of the result, must be executed in the on-chip RAM.

Since the on-chip program to be downloaded is embedded in the on-chip RAM, make sure the on-

chip program and procedure program do not overlap. Figure 21.12 shows the area of the on-chip

program to be downloaded.

H'FFBFFF

Programming/erasing

program entry

System use area

(15 bytes)

DPFR

(Return value: 1 byte)

FTDAR setting

FTDAR setting + 32 bytes

FTDAR setting + 16 bytes

Initialization program

entry

Initialization +

programming program

Initialization +

erasing program

RAM emulation area or

area that can be used

by user

Area that can be used

by user

Area to be

downloaded

(size: 4 kbytes)

Unusable area during

programming/erasing

FTDAR setting + 4 kbytes

Figure 21.12 RAM Map when Programming/Erasing is Executed

H8SX/1663 데이터시트(PDF) 964 Page - Renesas Technology Corp