H8SXSLASH1663 datasheet(303/1158 Pages) RENESAS

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Section 6 Bus Controller (BSC)

Rev.1.00 Jun. 07, 2006 Page 251 of 1102

REJ09B0294-0100

(3) Refresh and All-Module Clock Stop Mode

This LSI is entered in all-module clock stop mode by the following operation: Stop the clocks of

all on-chip peripheral modules by setting the ACSE bit in MSTPCR to 1 (MSTPCRA, MSTPCRB

= H'FFFFFFFF) or run only the 8-bit timer (MSTPCRA, MSTPCRB = H'F[C to F]FFFFFF), then

execute the SLEEP instruction to enter the sleep mode.

In all-module clock stop mode, clocks for the bus controller and I/O ports are stopped. Since the

clock for the bus controller is stopped, a CBR refresh cycle cannot be performed. When external

DRAM is used and the contents of the DRAM in sleep mode should be held, clear the ACSE bit in

MSTPCE to 0.

For details, see section 23.2.2, Module Stop Control Registers A and B (MSTPCR and

MSTPCRB).

6.10.13

DRAM Interface and Single Address Transfer by DMAC

When fast-page mode (BE = 1) is set for the DRAM space, either fast-page access or full access

can be selected, by the setting of bit DDS in DRAMCR, for the single address transfer by the

DMAC where the DRAM space is specified as the transfer source or destination. At the same

time, the output timing of the

DACK and BS signals is changed. When BE = 0, full access to the

DRAM space is performed by single address transfer regardless of the setting of bit DDS.

However, the output timing of the

DACK and BS signals can be changed by the setting of bit

DDS.

The assertion timing of the

DACK signal can be changed by bit DKC in BCR1.

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