H8SXSLASH1663R datasheet(805/1504 Pages) RENESAS

부품명	H8SX/1663R

상세설명	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

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Section 14 16-Bit Timer Pulse Unit (TPU)

Rev. 2.00 Sep. 24, 2008 Page 773 of 1468

REJ09B0412-0200

14.10.11 Conflict between Overflow/Underflow and Counter Clearing

If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is

not set and TCNT clearing takes precedence.

Figure 14.54 shows the operation timing when a TGR compare match is specified as the clearing

source, and H'FFFF is set in TGR.

Counter clear

signal

H'0000

TCNT input

clock

TCNT

TGF flag

TCFV flag

H'FFFF

Disabled

Figure 14.54 Conflict between Overflow and Counter Clearing

14.10.12 Conflict between TCNT Write and Overflow/Underflow

If an overflow/underflow occurs due to increment/decrement in the T2 state of a TCNT write

cycle, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set.

Figure 14.55 shows the operation timing when there is conflict between TCNT write and

overflow.

TCNT

H'FFFF

TCFV flag

Address

Write

TCNT address

TCNT write data

TGR write cycle

Figure 14.55 Conflict between TCNT Write and Overflow

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