H8SXSLASH1663R datasheet(88/1504 Pages) RENESAS

88 / 1504 page

Section 2 CPU

Rev. 2.00 Sep. 24, 2008 Page 56 of 1468

REJ09B0412-0200

2.7.2

Table of Instructions Classified by Function

Tables 2.4 to 2.11 summarize the instructions in each functional category. The notation used in

these tables is defined in table 2.3.

Table 2.3

Operation Notation

Description

General register (destination)*

General register (source)*

General register*

ERn

General register (32-bit register)

(EAd)

Destination operand

(EAs)

Source operand

EXR

Extended control register

CCR

Condition-code register

VBR

Vector base register

SBR

Short address base register

N (negative) flag in CCR

Z (zero) flag in CCR

V (overflow) flag in CCR

C (carry) flag in CCR

Program counter

Stack pointer

#IMM

Immediate data

disp

Displacement

Addition

−

Subtraction

Multiplication

Division

∧

Logical AND

∨

Logical OR

⊕

Logical exclusive OR

→

Move

∼

Logical not (logical complement)

:8/:16/:24/:32

8-, 16-, 24-, or 32-bit length

Note:

General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0

to R7, E0 to E7), and 32-bit registers (ER0 to ER7).

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