H8SXSLASH1663R datasheet(1256/1504 Pages) RENESAS

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Section 27 Clock Pulse Generator

Rev. 2.00 Sep. 24, 2008 Page 1224 of 1468

REJ09B0412-0200

Bit

Bit Name

Initial

Value

R/W

Description

13 to 11



All 0

R/W

Reserved

Although these bits are readable/writable, only 0 should

be written to.

ICK2

ICK1

ICK0

R/W

System Clock (I

φ) Select

These bits select the frequency of the system clock

provided to the CPU, EXDMAC, DMAC, and DTC. The

ratio to the input clock is as follows:

ICK (2:0) MD_CLK = 0

MD_CLK = 1

000:

× 4

× 2

001:

× 2

× 1

010:

× 1

× 1/2

011:

× 1/2

Setting prohibited

1XX:

Setting prohibited

The frequencies of the peripheral module clock and

external bus clock change to the same frequency as the

system clock if the frequency of the system clock is

lower than that of the two clocks.



R/W

Reserved

Although this bit is readable/writable, only 0 should be

written to.

PCK2

PCK1

PCK0

R/W

Peripheral Module Clock (P

φ) Select

These bits select the frequency of the peripheral

module clock. The ratio to the input clock is as follows:

PCK (2:0) MD_CLK = 0

MD_CLK = 1

000:

× 4

× 2

001:

× 2

× 1

010:

× 1

× 1/2

011:

× 1/2

Setting prohibited

1XX:

Setting prohibited

The frequency of the peripheral module clock should be

lower than that of the system clock. Though these bits

can be set so as to make the frequency of the

peripheral module clock higher than that of the system

clock, the clocks will have the same frequency in reality.

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