H8SXSLASH1663R datasheet(132/1504 Pages) RENESAS

132 / 1504 page

Section 4 Resets

Rev. 2.00 Sep. 24, 2008 Page 100 of 1468

REJ09B0412-0200

4.3.2

Reset Control/Status Register (RSTCSR)

RSTCSR controls an internal reset signal generated by the watchdog timer and selects the internal

reset signal type. RSTCSR is initialized to H’1F by a pin reset or a deep software standby reset,

but not by the internal reset signal generated by a WDT overflow.

Bit

Bit name

Initial value:

R/W:

WOVF

R/(W)*

RSTE

R/W



R/W



Note: * Only 0 can be written to clear the flag.

Bit

Bit Name

Initial

Value

R/W

Description

WOVF

R/(W)*

Watchdog Timer Overflow Flag

This bit is set when TCNT overflows in watchdog timer mode,

but not set in interval timer mode. Only 0 can be written to.

[Setting condition]

When TCNT overflows (H’FF

→ H’00) in watchdog timer

mode.

[Clearing condition]

When this bit is read as 1 and then written by 0.

RSTE

R/W

Reset Enable

Selects whether or not the LSI internal state is reset by a

TCNT overflow in watchdog timer mode.

0: Internal state is not reset when TCNT overflows. (Although

this LSI internal state is not reset, TCNT and TCSR of the

WDT are reset.)

1: Internal state is reset when TCNT overflows.



R/W

Reserved

Although this bit is readable/writable, operation is not affected

by this bit.

4 to 0



Reserved

These are read-only bits but cannot be modified.

Note:

Only 0 can be written to clear the flag.

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