H8SXSLASH1663R datasheet(198/1504 Pages) RENESAS

198 / 1504 page

Section 7 Interrupt Controller

Rev. 2.00 Sep. 24, 2008 Page 166 of 1468

REJ09B0412-0200

the condition that has held the activation source is cancelled (CPUPCE = 1 and the value of the

bits CPUP2 to CPUP0 is greater than that of the bits EDMAP2 to EDMAP0). When different

priority level is assigned for each channel, channels having higher priority than CPU continue

transferring processing, while activation sources for channels with lower priority should only be

held.

There are two methods for assigning the priority level to the CPU by the IPSETE bit in CPUPCR.

Setting the IPSETE bit to 1 enables a function to automatically assign the value of the interrupt

mask bit of the CPU to the CPU priority level. Clearing the IPSETE bit to 0 disables the function

to automatically assign the priority level. Therefore, the priority level is assigned directly by

software rewriting bits CPUP2 to CPUP0. Even if the IPSETE bit is 1, the priority level of the

CPU is software assignable by rewriting the interrupt mask bit of the CPU (I bit in CCR or I2 to I0

bits in EXR).

The priority level which is automatically assigned when the IPSETE bit is 1 differs according to

the interrupt control mode.

In interrupt control mode 0, the I bit in CCR of the CPU is reflected in bit CPUP2. Bits CPUP1

and CPUP0 are fixed 0. In interrupt control mode 2, the values of bits I2 to I0 in EXR of the CPU

are reflected in bits CPUP2 to CPUP0.

Table 7.7 shows the CPU priority control.

Table 7.7

CPU Priority Control

Control Status

Interrupt

Control

Mode

Interrupt

Priority

Interrupt

Mask Bit

IPSETE in

CPUPCR

CPUP2 to CPUP0

Updating of CPUP2

to CPUP0

Default

I = any

B'111 to B'000

Enabled

I = 0

B'000

Disabled

I = 1

B'100

IPR setting

I2 to I0

B'111 to B'000

Enabled

I2 to I0

Disabled

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