H8SXSLASH1663R datasheet(234/1504 Pages) RENESAS

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Section 9 Bus Controller (BSC)

Rev. 2.00 Sep. 24, 2008 Page 202 of 1468

REJ09B0412-0200

9.2.8

Bus Control Register 2 (BCR2)

BCR2 is used for bus arbitration control of the CPU, DMAC, EXDMAC, and DTC, and

enabling/disabling of the write data buffer function to the peripheral modules.

Bit

Bit Name

Initial Value

R/W



EBCCS

R/W

IBCCS

R/W



R/W

PWDBE

R/W

Bit

Bit Name

Initial

Value

R/W

Description

7, 6



All 0

Reserved

These are read-only bits and cannot be modified.

EBCCS

R/W

External Bus Cycle Control Select

Selects the method for external bus arbitration.

0: Releases the bus depending on the priority

1: Executes the bus cycle alternatively when a conflict

occurs between a bus request by the EXDMAC,

external bus master or refresh bus and a request for

an external space access by the CPU, DMAC, or

DTC.

IBCCS

R/W

Internal Bus Cycle Control Select

Selects the internal bus arbiter function.

0: Releases the bus mastership according to the priority

1: Executes the bus cycles alternatively when a CPU

bus mastership request conflicts with a DMAC or

DTC bus mastership request

3, 2



All 0

Reserved

These are read-only bits and cannot be modified.



R/W

Reserved

This bit is always read as 1. The write value should

always be 1.

PWDBE

R/W

Peripheral Module Write Data Buffer Enable

Specifies whether or not to use the write data buffer

function for the peripheral module write cycles.

0: Write data buffer function not used

1: Write data buffer function used

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