H8SXSLASH1663R datasheet(240/1504 Pages) RENESAS

부품명	H8SX/1663R

상세설명	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

PDF	1504 Pages

Scroll/Zoom	100%

제조업체	RENESAS [Renesas Technology Corp]

홈페이지	http://www.renesas.com

Logo

240 / 1504 page

Section 9 Bus Controller (BSC)

Rev. 2.00 Sep. 24, 2008 Page 208 of 1468

REJ09B0412-0200

9.2.13

DRAM Control Register (DRAMCR)

DRAMCR specifies the DRAM/SDRAM interface. Rewrite this register while the

DRAM/SDRAM is not accessed.

Bit

Bit Name

Initial Value

R/W

DRAME

R/W

DTYPE

R/W



OEE

R/W

RAST

R/W



CAST

R/W

Bit

Bit Name

Initial Value

R/W

RCDM

R/W

DDS

R/W

EDDS

R/W



R/W

MXC1

R/W

MXC0

R/W

Bit

Bit Name

Initial

Value

R/W

Description

DRAME

R/W

Area 2 DRAM Interface Select

Selects whether or not area 2 is specified as the

DRAM/SDRAM interface. When this bit is set to 1,

select the type of DRAM to be used in area 2 with the

DTYPE bit. When this bit is set to 1, the BCSEL2 bit in

SRAMCR should be set to 0.

0: Basic bus interface or byte-control SRAM interface

1: DRAM/SDRAM interface

DTYPE

R/W

DRAM Select

Selects the type of DRAM to be used in area 2.

0: DRAM is used in area 2

1: SDRAM is used in area 2

13, 12



All 0

Reserved

The initial value should not be changed.

H8SX/1663R 데이터시트(PDF) 240 Page - Renesas Technology Corp

H8SX/1663R 데이터시트(HTML) 240 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

데이터시트 다운로드

링크 URL