H8SXSLASH1663R datasheet(246/1504 Pages) RENESAS

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Section 9 Bus Controller (BSC)

Rev. 2.00 Sep. 24, 2008 Page 214 of 1468

REJ09B0412-0200

9.2.15

Synchronous DRAM Control Register (SDCR)

SDCR specifies the settings for the SDRAM interface (when the DTYPE bit in DRAMCR is set

to 1). Rewrite this register while the SDRAM is not accessed. When the SDRAM interface is not

used, the initial value must not be changed.

Bit

Bit Name

Initial Value

R/W

MRSE

R/W



R/W



R/W



R/W

Bit

Bit Name

Initial Value

R/W

CKSPE

R/W



TRWL

R/W

Bit

Bit Name

Initial

Value

R/W

Description

MRSE

R/W

Mode Register Set Enable

Enables the setting in the SDRAM mode register. See

section 9.11.14, Setting SDRAM Mode Register.

0: Disables to set the SDRAM mode register

1: Enables to set the SDRAM mode register

14 to 12



All 0

Reserved

These bits are always read as 0. The initial value

should not be changed.

11, 10



R/W

Reserved

The initial value should not be changed.



R/W

Reserved

The initial value should not be changed.

CKSPE

R/W

Clock Suspend Enable

Enables the clock suspend mode in which read data

output cycles are extended. Setting this bit to 1 extends

cycles in which read data is output from SDRAM.

0: Disables the clock suspend mode

1: Enables the clock suspend mode

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