H8SXSLASH1663R datasheet(257/1504 Pages) RENESAS

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Section 9 Bus Controller (BSC)

Rev. 2.00 Sep. 24, 2008 Page 225 of 1468

REJ09B0412-0200

9.5

External Bus

9.5.1

Input/Output Pins

Table 9.2 shows the pin configuration of the bus controller and table 9.3 shows the pin functions

on each interface.

Table 9.2

Pin Configuration

Name

Symbol

I/O

Function

Bus cycle start

Output

Signal indicating that the bus cycle has started

Address strobe/

address hold

AS/AH

Output

•

Strobe signal indicating that the basic bus, byte control

SRAM, or burst ROM space is accessed and address

output on address bus is enabled

•

Signal to hold the address during access to the

address/data multiplexed I/O interface

Read strobe

Output

Strobe signal indicating that the basic bus, byte control

SRAM, burst ROM, or address/data multiplexed I/O space

is being read

Read/write

RD/

Output

•

Signal indicating the input or output direction

•

Write enable signal of the SRAM during access to the

byte control SRAM space

Low-high write/

lower-upper byte

select

LHWR/LUB

Output

•

Strobe signal indicating that the basic bus, burst ROM,

or address/data multiplexed I/O space is written to,

and the upper byte (D15 to D8) of data bus is enabled

•

Strobe signal indicating that the byte control SRAM

space is accessed, and the upper byte (D15 to D8) of

data bus is enabled

Low-low write/

lower-lower byte

select

LLWR/LLB

Output

•

Strobe signal indicating that the basic bus, burst ROM,

or address/data multiplexed I/O space is written to,

and the lower byte (D7 to D0) of data bus is enabled

•

Strobe signal indicating that the byte control SRAM

space is accessed, and the lower byte (D7 to D0) of

data bus is enabled

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