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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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H8SX/1663R 데이터시트(PDF) 288 Page - Renesas Technology Corp |
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H8SX/1663R 데이터시트(HTML) 288 Page - Renesas Technology Corp |
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288 / 1504 page  Section 9 Bus Controller (BSC) Rev. 2.00 Sep. 24, 2008 Page 256 of 1468 REJ09B0412-0200 9.6.7 DACK and EDACK Signal Output Timing When the DMAC or EXDMAC transfers data in single address mode, the output timing of the DACK and EDACK signals can be changed by the DKC and EDKC bits in BCR1. Figure 9.24 shows the output timing of the DACK and EDACK signals. The DACK and EDACK signals are asserted a half cycle earlier by setting the DKC or EDKC bits to 1. T 1 T 2 Bus cycle B φ Address bus Write data Write Read data Read CSn AS RD Data bus Data bus LHWR, LLWR BS RD/ WR DKC, EDCK = 0 DKC, EDCK = 1 DACK or EDACK Notes: 1. n = 7 to 0 2. RDNn = 0 Figure 9.24 DACK and EDACK Signal Output Timing |
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