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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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H8SX/1663M 데이터시트(PDF) 376 Page - Renesas Technology Corp |
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H8SX/1663M 데이터시트(HTML) 376 Page - Renesas Technology Corp |
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376 / 1504 page  Section 9 Bus Controller (BSC) Rev. 2.00 Sep. 24, 2008 Page 344 of 1468 REJ09B0412-0200 T p T r T c1 T c2 Address bus Row address Cloumn address SDRAM φ CS Precharge-sel RAS CAS WE CKE PALL ACTV WRIT NOP DQMLU DQMLL D7 to D0 BS RD/ WR D15 to D8 Row address High DACK or EDACK Figure 9.90 Output Timing Example of DACK and EDACK when DKC = 1 or EDKC = 1 and DDS = 0 or EDDS = 0 (Write) 9.11.16 EXDMAC Cluster Transfer Using an EXDMAC cluster transfer mode, data can be read from or written to consecutively. For details, see section 11, EXDMA Controller (EXDMAC). Figures 9.91 and 9.92 show a read/write timing using a cluster transfer. For 1-cycle read or write, set the BE bit in DRAMCR to 1, clear the TRWL bit in SDCR to 0, and set the CAS latency to 2. During a read cycle, the clock suspend mode cannot be used. Do not change the bus controller register settings during a cluster transfer. |
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