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H8SX/1663M 데이터시트(PDF) 384 Page - Renesas Technology Corp

부품명 H8SX/1663M
상세설명  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
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제조업체  RENESAS [Renesas Technology Corp]
홈페이지  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX/1663M 데이터시트(HTML) 384 Page - Renesas Technology Corp

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Section 9 Bus Controller (BSC)
Rev. 2.00 Sep. 24, 2008 Page 352 of 1468
REJ09B0412-0200
(4)
External Access after Single Address Transfer Write
If an external access occurs after a single address transfer write while bit IDLS3 in IDLCR is set
to 1, idle cycles specified by bits IDLCA1 and IDLCA0 are inserted at the start of the external
access (n = 0 to 7).
Figure 9.96 shows an example of the operation in this case. In this example, bus cycle A is a
single address transfer (write cycle) and bus cycle B is a CPU write cycle. In (a), an idle cycle is
not inserted, and a conflict occurs in bus cycle B between the external device write data and this
LSI write data. In (b), an idle cycle is inserted, and a data conflict is prevented.
Output floating
time is long.
Data conflict
Bus cycle A
Bus cycle B
(a) No idle cycle inserted
(IDLS3 = 0)
B
φ
Address bus
CS (area A)
CS (area B)
LLWR
DACK
Data bus
T
1
T
2
T
3
T
1
T
2
(b) Idle cycle inserted
Bus cycle A
Bus cycle B
T
1
T
2
T
3
T
1
T
i
T
2
(IDLS3 = 1, IDLCA1 = 0, IDLCA0 = 0)
Figure 9.96 Example of Idle Cycle Operation (Write after Single Address Transfer Write)



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