H8SXSLASH1663M datasheet(398/1504 Pages) RENESAS

398 / 1504 page

Section 9 Bus Controller (BSC)

Rev. 2.00 Sep. 24, 2008 Page 366 of 1468

REJ09B0412-0200

9.15.2

Write Data Buffer Function for Peripheral Modules

This LSI has a write data buffer function for the peripheral module access. Using the write data

buffer function enables peripheral module writes and on-chip memory or external access to be

executed in parallel. The write data buffer function is made available by setting the PWDBE bit in

BCR2 to 1. For details on the on-chip peripheral module registers, see table 9.34, Number of

Access Cycles for Registers of On-Chip Peripheral Modules in section 9.14, Internal Bus.

Figure 9.105 shows an example of the timing when the write data buffer function is used. When

this function is used, if an internal I/O register write continues for two cycles or longer and then

there is an on-chip RAM, an on-chip ROM, or an external access, internal I/O register write only

is performed in the first two cycles. However, from the next cycle onward an internal memory or

an external access and internal I/O register write are executed in parallel rather than waiting until

it ends.

On-chip

memory

read

Peripheral module write

Peripheral module address

Internal

address bus

Internal I/O

address bus

Internal I/O

data bus

Figure 9.105 Example of Timing when Peripheral Module

Write Data Buffer Function is Used

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