H8SXSLASH1663M datasheet(500/1504 Pages) RENESAS

500 / 1504 page

Section 11 EXDMA Controller (EXDMAC)

Rev. 2.00 Sep. 24, 2008 Page 468 of 1468

REJ09B0412-0200

Bit

Bit Name

Initial

value

R/W

Description

ACT

Active State

Indicates the operation state of the corresponding

channel.

0: Transfer request wait state or transfer disabled state

(DTE = 0)

1: Active state

22 to 20



All 0

Reserved

They are always read as 0 and cannot be modified.

ERRF

R/(W)*

System Error Flag

Flag that indicates the occurrence of an address error

or NMI interrupt. This bit is only enabled in EDMDR_0.

When this bit is set to 1, write to the DTE bit for all

channels is disabled. This bit is reserved in EDMDR_1

to EDMDR_3. They are always read as 0 and cannot

be modified.

0: Address error or NMI interrupt is not generated

1: Address error or NMI interrupt is generated

[Clearing condition]

• Writing 0 to ERRF after reading ERRF = 1

[Setting condition]

• When an address error or NMI interrupt occurred

However, when an address error or an NMI interrupt

has been generated in EXDMAC module stop mode,

this bit is not set to 1.



Reserved

They are always read as 0 and cannot be modified.

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