H8SXSLASH1663M datasheet(511/1504 Pages) RENESAS

511 / 1504 page

Section 11 EXDMA Controller (EXDMAC)

Rev. 2.00 Sep. 24, 2008 Page 479 of 1468

REJ09B0412-0200

11.3.8

Cluster Buffer Registers 0 to 7 (CLSBR0 to CLSBR7)

CLSBR0 to CLSBR7 are 32-bit readable/writable registers that store the transfer data. The transfer

data is stored in order from CLSBR0 to CLSBR7 in cluster transfer mode. The data stored in

cluster transfer mode or by the CPU write operation is held until the next cluster transfer or CPU

write operation is performed.

When reading the data stored in cluster transfer mode by the CPU, check the completion of cluster

transfer and then perform only a cluster-size read specified for the cluster transfer. Data with

another size is undefined.

In cluster transfer mode, the same CLSBR is used for all channels. When the CPU write operation

to CLSBR conflicts with cluster transfer, the contents of transferred data are not guaranteed. When

cluster transfer read/write address mode is specified and if another channel is set for cluster

transfer, the transferred data may be overwritten.

Undefined

R/W

Undefined

R/W

Undefined

R/W

Undefined

R/W

Undefined

R/W

Undefined

R/W

Undefined

R/W

Undefined

R/W

Bit

Bit Name

Initial Value

R/W

Undefined

R/W

Undefined

R/W

Undefined

R/W

Undefined

R/W

Undefined

R/W

Undefined

R/W

Undefined

R/W

Undefined

R/W

Bit

Bit Name

Initial Value

R/W

Undefined

R/W

Undefined

R/W

Undefined

R/W

Undefined

R/W

Undefined

R/W

Undefined

R/W

Undefined

R/W

Undefined

R/W

Bit

Bit Name

Initial Value

R/W

Undefined

R/W

Undefined

R/W

Undefined

R/W

Undefined

R/W

Undefined

R/W

Undefined

R/W

Undefined

R/W

Undefined

R/W

Bit

Bit Name

Initial Value

R/W

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